Jean Mermet

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

VHDL for Simulation, Synthesis and Formal Proofs of Hardware

This book presents the perspective of the project on a Paradigm Unifying System Specification Environments for proven Electronic design (PUS SEE) as conceived in the course of the research during 2002 -2003. The initial statement of the research was formulated as follows: The objective of PUSSEE is to introduce the formal proof of system properties throughout a modular system design methodology that integrates sub-systems co-verification with system refinement and reusability of virtual system components. This will be done by combining the UML and B languages to allow the verification of system specifications through the composition of proven sub-systems (in particular interfaces, using the VSIAISLIF standard). The link of B with C, VHDL and SystemC will extend the correct-by-construction design process to lower system-on-chip (SoC) development stages. Prototype tools will be developed for the code generation from UML and B, and existing B verification tools will be extended to support IP reuse, according to the VSI Alliance work. The methodology and tools will be validated through the development of three industrial applications: a wireless mobile terminal-a telecom system-on-chip based on HIPERLANI2 protocol and an anti-collision module for automobiles. The problem was known to be hard and the scope ambitious. But the seventeen chapters that follow, describing the main results obtained demonstrate the success of the research, acknowledged by the European reviewers. They are released to allow the largest audience to learn and take benefit of.

UML-B Specification for Proven Embedded Systems Design

Peter J. Ashenden

Ralf Seepold

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

Jean Mermet

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