High Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings

Message from the General Co-chairs It is our honor and pleasure as General Co-chairs to welcome you to the p- ceedings of HiPEAC 2010 which was held in Pisa. This was the ?fth HiPEAC conference, following in the strong tradition of the ?rst conference in Barcelona in 2005 and the subsequent conferences in Ghent (2007), Goteborg (2008), and Paphos (2009). HiPEAC2010o?eredarichanddiversesetoftechnicalandnon-technical- tivities. The technical activities included most importantly another strong te- nical program, and in addition, eight workshops and ?ve tutorials, all central to the HiPEAC network roadmap. The workshops explored multi-cores, simu- tion and performance evaluation, compiler and optimizations, design reliability, recon?gurable computing, interconnection networks,operating system and c- puter architecture codesign. The tutorials dealt with statistical methodology to evaluate program speed-ups, design for reliability, how to teach introductory computer architecture and programming, programming FPGA-based accele- tors and adaptability. We were particularly fortunate to have two keynote addresses, one by Bob Iannucci, formerly from Nokia, on how data center thinking can be e?ectively ushered into the embedded system domain, and one by Roger Espasa from Intel on the Larrabee Architecture. The non-technical activities re?ected the academic, historical, and cultural charm of Pisa, a major center of Tuscany, and we hope the participants took advantage of our scheduled guided tour of historical Pisa and the conference banquet in a historic villa.